Researchers at the University of Pittsburgh have developed a high throughput and scalable integrated photonic matrix-matrix multiplier architecture. This technology addresses the growing computational needs in artificial intelligence and machine learning by enabling high efficiency, mid- to low-resolution (5 to 8-bits), and massively parallel matrix-matrix multiplication (MMM). The architecture uses a novel 2D photonic crossbar array to perform N^2 dot products in parallel, achieving clock speeds exceeding tens of GHz. This advancement could revolutionize computational efficiency and energy savings in AI and ML applications.
Description
The integrated photonic architecture encodes matrix elements in the amplitude and phase of the optical field and uses a 2D photonic crossbar array to uniformly distribute and overlap optical fields, computing N^2 optical dot products in parallel. The modulation occurs in the optical domain, allowing for high-speed multiply and accumulate operations (MACs) using an integrated imaging system like a charge-coupled device (CCD) or on-chip photodetectors. This method provides significant energy savings during analog-to-digital conversion (ADC) compared to prior analog computing approaches. Additionally, the architecture supports multiplexing computation through multiple wavelengths, unique to the optical domain.
Applications
• Artificial intelligence
• Machine learning
• High-performance computing
• Optical computing
Advantages
The integrated photonic matrix-matrix multiplier architecture offers significant benefits, including high-speed computation with speeds exceeding tens of GHz, substantial energy savings during analog-to-digital conversion, and scalability for massively parallel matrix-matrix multiplication. Additionally, it supports multiplexing computation through multiple wavelengths within the same physical circuit, making it a highly efficient and versatile solution for artificial intelligence, machine learning, and high-performance computing applications.
Invention Readiness
The concept is currently in the development stage, with ongoing efforts to refine and optimize the architecture. The technology uses a 2D photonic crossbar array to perform N^2 dot products in a single clock cycle, achieving speeds exceeding tens of GHz. Multiply and accumulate operations (MACs) are performed at optical speeds using an integrated imaging system such as a charge-coupled device (CCD), which operates at much lower speeds (MHz or kHz), providing significant energy savings during analog-to-digital conversion (ADC). Further experimental work is focused on optimizing the optical interference patterns, improving the efficiency of the photonic crossbar array, and integrating the system on a chip for scalable computing applications.
IP Status
https://patents.google.com/patent/US20240370050A1
