Controlling electron confinement within nanoscale environments is essential to a range of science and technology fields, and is especially important to the creation of novel electronic devices. Confinement becomes increasingly challenging as the dimensionality and scale are reduced. Various methods for creating nanoelectronics include self-assembled molecule layers or template synthesis using quantum dots, carbon nanotubes, nanowires, or nanocrystals. Other top-down approaches use tools such as electron-beam lithography, atomic-force microscopy, nanoimprint lithography, dip-pen nanolithography, and scanning tunneling microscopy. These lithographic procedures, however, are complex and irreversible. The rapidly developing field of nanoelectronics stands to benefit greatly from a simple and reversible method of creation.
Description
Researchers at the University of Pittsburgh have developed a novel method of creating nanoscale electronics with the potential to create the smallest electrical devices demonstrated to date while circumventing the need to use more complicated lithographic procedures. This is accomplished by inducing a “polarization catastrophe” that produces a quasi-two-dimensional electron gas at the interface between two polar insulators, LaAlO3 and SrTiO3. Nanoscale conducting regions are created and erased using voltages applied by a conducting AFM probe, which can then create various multi-terminal devices. This writing and erasing process allows for remarkable versatility in the creation of tunnel junctions and field-effect transistors with spatial dimensions comparable to single-wall nanotubes and holds the potential to revolutionize the electrical device market.
Applications
· Logic and memory applications
· Low-dimensional transport such as Coulomb blockades, resonant tunneling, and single-electron transistor behavior
· Nanoscale magnetism and spin resonance
· Nanoscale biological, chemical, or electrical sensors
· Self-referential measurements
Advantages
· Circumvents use of more complicated lithographic procedures
· Reversible and erasable
Invention Readiness
Successful protoypes
IP Status
https://patents.google.com/patent/US20130048950A1
