Power Efficient, High Bandwidth Chip-to-Chip Signaling Using Fixed Load Encoding

Description

This invention is a new signaling system for high speed, short haul (1cm-1m), digital communications links that is applicable to printed circuit board, computer backplane and point-to-point applications operating at multi-gigabit data rates. This new design is a significant improvement over current differential signaling standards. This system substantially expands the information carrying capacity of these links while retaining the advantages of lower power-supply noise, fast current steering drivers, constant load and common mode noise rejection that characterizes differential links. It is possible to design links that use 30% to 40% less chip area and electrical power when compared to an equivalent differential link.

IP Status

https://patents.google.com/patent/US7358869B1

Quick Facts:
Reference Number
00825
Technology Type
Engineering Technology
Technology Subtype
Other Engineering Technology
Lead Inventor
Donald Chiarulli
Department
Electrical and Computer Engineering
All Tech Innovators
Donald M. ChiarulliSteven P. Levitan
Date Submitted
2003-06-24