University of Pittsburgh researchers have developed an adaptive read voltage scheme for FeFET memory, addressing the challenge of limited retention time due to polarization loss in the ferroelectric layer. This innovative scheme compensates for polarization loss by regulating the read voltage based on the output of a refresh trigger, which changes according to the polarization level of the FeFETs. This technology promises to enhance the performance and reliability of FeFET memory, making it a valuable advancement in the field of non-volatile memory.
Description
FeFET memory is known for its non-volatile properties, but its retention time is limited due to the gradual reduction in the polarization level of the ferroelectric layer. This reduction causes a smaller readout difference between the on-off states of the FeFET. The proposed adaptive read voltage scheme compensates for this loss by using the refresh trigger's output to determine a specific read voltage for each memory row. The scheme consists of two voltage dividers built with CMOS transistors. The first voltage divider includes two NMOS transistors, one of which takes the refresh trigger's output as gate voltage, while the other's gate voltage is connected to a predetermined reference voltage. The secondary voltage divider, consisting of a PMOS and an NMOS transistor, determines the final output used as the read voltage based on the first voltage divider's output.
Applications
• Non-volatile memory systems
• Data storage solutions
• Memory devices in consumer electronics
• Industrial and automotive memory applications
Advantages
The adaptive read voltage scheme provides specific read voltage for each block of the memory, enhancing the performance and reliability of FeFET memory. By compensating for polarization loss, this technology ensures a more stable and longer retention time for data storage. The use of CMOS transistors in the voltage dividers makes the scheme compatible with existing semiconductor manufacturing processes.
Invention Readiness
The adaptive read voltage scheme has been developed and tested in vitro, demonstrating its effectiveness in compensating for polarization loss in FeFET memory. The technology is ready for further development and commercialization, with potential applications in various memory devices and systems.
IP Status
https://patents.google.com/patent/US10269406B2
